1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device having a flip-flop circuit or circuits.
2. Description of Related Art
Conventionally, flip-flop circuits have been widely used in integrated circuits, such as LSI devices. Flip-flop circuits are classified into those of synchronous type and those of asynchronous type. A synchronous flip-flop circuit changes the output thereof in synchronization with a clock input. Synchronous flip-flop circuits include circuits of various types, such as a master-slave flip-flop circuit and a pulse-triggered flip-flop circuit.
Incidentally, as functions required of a synchronous flip-flop circuit, there are asynchronous clear and preset functions. These functions are intended to forcibly clear and preset the output node of a flip-flop circuit (hereinafter also referred to as a state retention node).
In a flip-flop circuit of master-slave type, clear and preset functions can be easily realized by adding a pull-down circuit or a pull-up circuit to the output node, as described in Japanese Patent Application Laid-Open No. 6-260902.
On the other hand, a flip-flop circuit of pulse-triggered type changes the output thereof only in a narrow pulse duration synchronized with a clock input. Conceivably, a pull-down circuit or a pull-up circuit may be added to the output node of such a pulse-triggered flip-flop circuit to clear or preset the output node.
In this case, however, a short circuit can occur in the output node depending on the state of input data. For this reason, in a pulse-triggered flip-flop circuit, it has been impossible to provide clear and preset functions by the same means as used in a master-slave flip-flop circuit.
It should be noted that the term “pulse-triggered flip-flop” as used herein refers to a flip-flop capable of changing the output thereof only in a relatively narrow pulse duration synchronized with a clock input.